Method to deliver in-dram ecc information through ddr bus

ABSTRACT

A data chip that may pollute data is disclosed. The data chip may include a data array, read circuitry to read raw data from the data array, and a buffer to store the raw data. Using a pollution pattern stored in a mask register, a data pollution engine may pollute the raw data. Transmission circuitry may then transmit the polluted data.

RELATED APPLICATION DATA

This application is a divisional of U.S. patent application Ser. No.15/410,752, filed Jan. 19, 2017, which claims the benefit of U.S.Provisional Patent Application Ser. No. 62/418,779, filed Nov. 7, 2016,both of which are incorporated by reference herein for all purposes.

This application is related to U.S. patent application Ser. No. ______,which is a divisional of U.S. patent application Ser. No. 15/410,752,filed Jan. 19, 2017, which claims the benefit of U.S. Provisional PatentApplication Ser. No. 62/418,779, filed Nov. 7, 2016, all of which areincorporated by reference for all purposes.

FIELD

The inventive concepts relate generally to memory, and more particularlyto providing error correcting capabilities without increasing the numberof data chips in a memory module.

BACKGROUND

In the future, memory modules may require in-Dynamic Random AccessMemory (DRAM) error correction. Combined with the use of narrowchannels, the overhead required for error correction may be increasing.For example, transitioning from wide channels to narrow channels maydouble the error correction overhead. Satisfying the reliability,availability, and serviceability (RAS) requirements for memory maybecome expensive. But discarding error correction capability entirelymay reduce the usability of the memory module.

A need remains for a way for to provide error correction capability in amemory module without increasing the overhead requirements for errorcorrection.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a machine with a memory and memory controller, according toan embodiment of the inventive concept.

FIG. 2 shows additional details of the machine of FIG. 1.

FIG. 3 shows details of a memory chip in the memory of FIG. 1.

FIG. 4 shows an example implementation of the XOR circuitry of FIG. 3.

FIG. 5 shows how data in the data chip of FIG. 3 may be polluted.

FIG. 6 shows a mask register in the data chip of FIG. 3 storingpollution patterns.

FIG. 7 shows details of the memory controller of FIG. 1.

FIG. 8 shows the memory controller of FIG. 1 performing a paritycalculation on data from the data chips in the memory of FIG. 1.

FIG. 9 shows the operation of the pollution pattern analysis circuitryof FIG. 7.

FIG. 10 shows the memory controller of FIG. 1 removing the pollutionpattern from the data received from a data chip.

FIG. 11 shows the parity circuitry of FIG. 7 calculating the data for adata chip whose data had a pollution pattern.

FIGS. 12A-12B show a flowchart of an example procedure for a data chipin the memory module of FIG. 1 to pollute data, according to anembodiment of the inventive concept.

FIG. 13 shows a flowchart of an example procedure for the data chip inthe memory module of FIG. 1 to be programmed with a pollution pattern,according to an embodiment of the inventive concept.

FIG. 14 shows a flowchart of an example procedure for the data chip inthe memory module of FIG. 1 to transmit original data to the memorycontroller of FIG. 1, according to an embodiment of the inventiveconcept.

FIGS. 15A-15B show a flowchart of an example procedure for the memorycontroller of FIG. 1 to perform error correction when a data chip in thememory module of FIG. 1 pollutes data using a pollution pattern,according to an embodiment of the inventive concept.

FIG. 16 shows a flowchart of an example procedure for the pollutionpattern analysis circuitry of FIG. 7 to identify which pollution patternwas used to pollute the data, according to an embodiment of theinventive concept.

FIG. 17 shows a flowchart of an example procedure for the errorcorrection circuitry of FIG. 7 to correct for the error in the data chipin the memory module of FIG. 1, according to an embodiment of theinventive concept.

FIG. 18 shows a flowchart of an example procedure for the memorycontroller of FIG. 1 to request the original data from the data chip inthe memory module of FIG. 1, according to an embodiment of the inventiveconcept.

DETAILED DESCRIPTION

Reference will now be made in detail to embodiments of the inventiveconcept, examples of which are illustrated in the accompanying drawings.In the following detailed description, numerous specific details are setforth to enable a thorough understanding of the inventive concept. Itshould be understood, however, that persons having ordinary skill in theart may practice the inventive concept without these specific details.In other instances, well-known methods, procedures, components,circuits, and networks have not been described in detail so as not tounnecessarily obscure aspects of the embodiments.

It will be understood that, although the terms first, second, etc. maybe used herein to describe various elements, these elements should notbe limited by these terms. These terms are only used to distinguish oneelement from another. For example, a first module could be termed asecond module, and, similarly, a second module could be termed a firstmodule, without departing from the scope of the inventive concept.

The terminology used in the description of the inventive concept hereinis for the purpose of describing particular embodiments only and is notintended to be limiting of the inventive concept. As used in thedescription of the inventive concept and the appended claims, thesingular forms “a,” “an,” and “the” are intended to include the pluralforms as well, unless the context clearly indicates otherwise. It willalso be understood that the term “and/or” as used herein refers to andencompasses any and all possible combinations of one or more of theassociated listed items. It will be further understood that the terms“comprises” and/or “comprising,” when used in this specification,specify the presence of stated features, integers, steps, operations,elements, and/or components, but do not preclude the presence oraddition of one or more other features, integers, steps, operations,elements, components, and/or groups thereof. The components and featuresof the drawings are not necessarily drawn to scale.

Embodiments of the inventive concept may reduce the Error CorrectingCode (ECC) overheads of Dynamic Random Access Memory (DRAM) modules.Embodiments of the inventive concept may be used with current Dual DataRate (DDR)-4 64 bit channels and future narrow (32 bits) DDR channels.Embodiments of the inventive concept may support any DRAM type,including ×4 (4 bit data width DRAM), ×8, ×16, or any other burst size.Embodiments of the inventive concept may also support memory modulesthat may support any number of bursts in a memory transaction, including8 burst (8 bursts per data chip per memory transaction), 16 burst, orany other number of bursts per memory transaction.

Future DRAM devices may use a narrower channel (32 bits, as opposed to64 bits) to maintain increasing throughput. There may be a correspondingincrease in the internal prefetch (16n vs. 8n) and external burst length(16n vs. 8n) as well.

But these changes may make it difficult to maintain current reliability,availability, and serviceability (RAS) features with a similar overheadto current Dynamin Random Access Memory (DRAM) Dual In-line MemoryModule (DIMM) devices. For example, current DDR-4 Error Correcting Codes(ECC) DRAM DIMMs use16 data chips and 2 error correcting code (ECC)chips for each channel. To maintain the same ECC coverage, future narrowDRAM channel may require 2 ECC chips to protect only 8 data chips:continuing to use only 2 ECC chips to protect 16 data chips may resultin downgraded ECC coverage.

In addition, future DRAM devices may use in-DRAM ECC to lower the biterror rate for DRAM devices. To deliver the in-DRAM ECC information fromDRAM device to memory controller, a dedicated or shared pin(s) isrequired. Instead, a method and mechanism to deliver the in-DRAM ECCinformation may be implemented by injecting additional errors when anerror is detected in DRAM devices. That is, the memory controller mayprogram DRAM chips in the same channel with different pollution patternsduring boot-up. Different DRAM chips in the same channel should havedifferent pollution patterns. Pollution pattern selection may bedifferent according to different chip set vendors. Pollution patternselection may results in different error coverage.

Embodiments of the inventive concept may use only 1 ECC chip, plusin-DRAM ECC, to provide basic reliability, availability, andserviceability (RAS) protection. For example:

-   -   In a DDR-4 64 bit channel using ×4 chips, the memory module may        include 16×4 data chips plus 1 ECC chip. Such an embodiment of        the inventive concept may offer error correction at ½ the        overhead of current error correction (which uses 16 data chips        plus 2 ECC chips).    -   In a DDR-4 64 bit channel using ×8 chips, the memory module may        include 8×8 data chips plus 1 ECC chip. Such an embodiment of        the inventive concept may offer basic chip kill (one data chip        failure), which current DDR-4×8 does not support.    -   In a DDR-4 64 bit channel using ×16 data chips, the memory        module may include 4×16 data chips plus 1 ECC chip. Such an        embodiment of the inventive concept may offer basic chip kill        (one data chip failure), which current DDR-4×16 does not        support.    -   For future 32 bit channel ×4 memory modules, the memory module        may include 8×4 data chips plus 1 ECC chip. Such an embodiment        of the inventive concept may offer error correction at ½ the        overhead of current error correction.    -   In general, for future memory modules with N bits per channel,        and ×4M data chips, the memory module may include N/4M×4M data        chips plus 1×M ECC chip.

When an in-DRAM ECC mechanism detects an internally uncorrectable error,the DRAM pollutes the data with these stored patterns. The datapollution may be accomplished by XORing the data on the chip with thepollution pattern when an internally uncorrectable error occurs.

The pollution pattern may use either a coarse or a fine granularity.With a fine grained approach, each pattern has 64 bits in a bit-to-bitmapping. This provides for more flexible information delivery, butrequires more bits (storage overhead) in the mask register, and is lessreliable. At a coarse granularity, each chip is given a repeating,pre-defined pattern. The means the pollution patterns are fixed andinflexible, but require fewer bits (storage overhead) in the maskregister and is more reliable.

The pollution pattern may be of any desired size. A recommended minimumpollution may be the size of one burst (although any pollution patternsize may be used so long as the memory controller may determine whichdata chip applied the pollution pattern). So, embodiments of theinventive concept may use 4 bit pollution patterns with ×4 data chips, 8bit pollution patterns with ×8 data chips, 16 bit pollution patternswith ×16 data chips, and so on. The pollution pattern may be as large asa memory transaction (the number of bits in a single burst multiplied bythe number of bursts in a memory transaction), which might vary from,for example, 32 bits (for 8 burst×4 data chips) to 256 bits (for 16burst×16 chips), or even larger.

In addition, a pollution pattern may be larger than one memorytransaction. But if the pollution pattern is larger than a single memorytransaction, detecting the pollution pattern may require two or morememory transaction to happen consecutively, which may be inefficient interms of performance.

Assuming the memory controller may detect the error, the memorycontroller may identify the error location (chip with the error) byusing the pollution patterns. The memory controller may then use parityacross chips to correct the error.

FIG. 1 shows a machine with a memory and memory controller, according toan embodiment of the inventive concept. In FIG. 1, machine 105 is shown.Machine 105 may be any desired machine, including without limitation adesktop or laptop computer, a server (either a standalone server or arack server), or any other device that may benefit from embodiments ofthe inventive concept. Machine 105 may also include devices such asspecialized portable computing devices, tablet computers, and evensmartphones. And while the described embodiments of the inventiveconcept refer to DRAM modules, embodiments of the inventive concept maybe applied to any form of memory that internally stores informationacross multiple chips (each of which may potentially be a separatesource of failure).

Machine 105, regardless of its specific form, may include processor 110,memory 115, storage device 120, and memory controller 125. Processor 110may be any variety of processor: for example, an Intel Xeon, Celeron,Itanium, or Atom processor, an AMD Opteron processor, an ARM processor,etc. While FIG. 1 shows a single processor, machine 105 may include anynumber of processors. Memory 115 may be any variety of memory, such asflash memory, Static Random Access Memory (SRAM), Persistent RandomAccess Memory, Ferroelectric Random Access Memory (FRAM), orNon-Volatile Random Access Memory (NVRAM), such as MagnetoresistiveRandom Access Memory (MRAM) etc. to which embodiments of the inventiveconcept are applicable, but is typically DRAM. Memory 115 may also beany desired combination of different memory types.

Storage device 120 may be any variety of storage device. Examples ofsuch devices may include Solid State Drives (SSDs), but other storageforms, such as hard disk drives or other long-term storage devices, arealso viable. In addition, memory 115 and storage device 120 may becombined: that is, embodiments of the inventive concept might notdistinguish between the concepts of short-term and long-term storage,but manage both in a single form factor. Finally, memory controller 125may manage communications between processor 110 and memory 115,requesting (and storing) information in memory 115 as appropriate.Memory controller 125 may integrated with processor 110 or in a separatechip.

FIG. 2 shows additional details of the machine of FIG. 1. Referring toFIG. 2, typically, machine 105 includes one or more processors 110,which may include memory controller 125 and clock 205, which may be usedto coordinate the operations of the components of machine 105.Processors 110 may also be coupled to memory 115, which may includerandom access memory (RAM), read-only memory (ROM), or other statepreserving media, as examples. Processors 110 may also be coupled tostorage devices 120, and to network connector 210, which may be, forexample, an Ethernet connector or a wireless connector. Processors 110may also be connected to a bus 215, to which may be attached userinterface 220 and input/output interface ports that may be managed usinginput/output engine 225, among other components.

FIG. 3 shows details of a memory chip in memory 115 of FIG. 1. In FIG.3, data chip 305 (which may be one of a plurality of chips in memory115) may include DRAM array 310, read circuitry 315, buffer 320, ECCengine 325, data pollution engine 330, mask register 335, demultiplexer340, and transmission circuitry 345. DRAM array 310 may store datawithin data chip 305. Read circuitry 315 may read data from DRAM array310. For example, read circuitry 315 may include sense amplifiers toread values from DRAM array 310. Buffer 320 may temporarily store thedata read from DRAM array 310 by read circuitry 315, while data chip 305does some processing. ECC engine 325 may attempt to perform errorcorrection on the data in buffer 320, if possible. ECC engine 325 mayprovide results of its operation to data pollution engine 330, so thatdata pollution engine 330 knows whether or not it needs to operate.

Data pollution engine 330 may pollute the data from buffer 320 whenneeded. As described below with reference to FIG. 5, pollution involvesmodifying the data in buffer 320 based on a pollution pattern. Datapollution may be performed by XORing a pollution pattern with the datain buffer 320: for example, using XOR circuitry 350. Alternatively, datapollution may be performed by simply replacing the data in buffer 320with the pollution pattern, regardless of what the error actually is. Ifthe data in buffer 320 exactly matches the pollution pattern, this factmight result in the system incorrectly “detecting” a false error, buthopefully the system may recover from such a situation. The pollutionpattern may be accessed from mask register 335. Data pollution engine330, like any other engine or circuitry described herein, may beimplemented in any desired manner. For example, the engines andcircuitry may be implemented using custom circuitry that implements thedesired functionality, or they may be implemented using an array such aField Programmable Gate Array (FPGA) or equivalent technology.

Because there may be situations in which memory controller 125 mightwant the raw (unpolluted) data from buffer 320, memory controller 125may send Memory Controller Disable signal 355 to data pollution engine330. Thus, data pollution engine 330 may operate to pollute the data ifECC engine 325 indicates that there was an uncorrectable error, unlessmemory controller 125 has sent Memory Controller Disable signal 355.

The output of data pollution engine 330 may then be sent todemultiplexer 340, which may select the appropriate data to output tomemory controller 125. Transmission circuitry 345 may then be used tosend the selected data to memory controller 125.

FIG. 4 shows an example implementation of XOR circuitry 350 of FIG. 3.In FIG. 4, XOR circuitry 350 may include logics 405 and 410, which maycontrol whether the original input value of the bit or its reverse valueis selected (using a signal splitter, a signal negation, and amultiplexer). Logics 405 and 410 may use control logic bits to determinewhat value to select.

As a general rule, the control logic will select the original value forthe bit, unless ECC engine 325 of FIG. 3 is unable to correct the errorand memory controller 125 of FIG. 1 has not sent Memory ControllerDisable signal 355 of FIG. 3. Thus, in terms of a logic equation, thecontrol logic (CL) may be thought of as the result of the pollutionpattern (PP) from mask register 335 of FIG. 3 AND (not Memory ControllerDisable signal 355 of FIG. 3) AND ECC engine 325 of FIG. 3. Table 415shows the values the control logic may take, given different values forthe pollution pattern, Memory Controller Disable signal 355 of FIG. 3,and ECC engine 325 of FIG. 3. But table 415 is merely illustrative, andgiven different inputs the control logic may be specified using otherlogic equations.

FIG. 5 shows how data in data chip 305 of FIG. 3 may be polluted. InFIG. 5, the values stored in buffer 320 of FIG. 3 is shown as including32 bits (although the width of buffer 320 of FIG. 3 may be any width: 32bits is merely exemplary). For simplicity of representation, FIG. 5shows the data arranged in two dimensions, although in practice buffer320 of FIG. 3 may be one-dimensional. Raw data 505 may be XORed withpollution pattern 510, producing polluted data 515. Note that each bitin polluted data 515 is the XOR of the corresponding bits in raw data505 and pollution pattern 510. But while FIG. 5 shows XORing raw data505 with pollution pattern 510, embodiments of the inventive concept maysupport any desired approach to pollute raw data 505

FIG. 6 shows mask register 335 of FIG. 3 in data chip 305 of FIG. 3storing pollution patterns. In FIG. 6, mask register 335 may includepollution patterns, such as pollution pattern 510. In some embodimentsof the inventive concept, memory controller 125 of FIG. 1 may programpollution pattern 510 into mask register 335 at boot up. As describedabove, by programming each data chip 305 of FIG. 3 (at least in the samedata channel) with a different pollution pattern, memory controller 125of FIG. 1 may then attempt to determine which data chip 305 of FIG. 3 isthe data chip with an error that could not be corrected using in-chipECC.

Alternatively, in other embodiments of the inventive concept, data chip305 of FIG. 3 may be pre-programmed (e.g., by the manufacturer) withvarious pollution patterns. For example, mask register 335 may bepre-programmed with pollution patterns 605, 610, 615, 620, 625, and 630,among others. While FIG. 6 shows six pre-programmed pollution patterns,typically the number of pre-programmed pollution patterns will be atleast as large as the number of data chips in the memory module(although fewer pollution patterns may be pre-programmed provided thateach data chip in the same data channel may be assigned a uniquepollution pattern). Memory controller 125 of FIG. 1 may then select apollution pattern for the data chip to use from pre-programmed pollutionpatterns 605, 610, 615, 620, 625, and 630.

Each pre-programmed pollution pattern may be assigned an identifier. Forexample, pre-programmed pollution pattern 605 may be assigned identifier635, pre-programmed pollution pattern 610 may be assigned identifier640, and so on for identifiers 645, 650, 655, and 660. Memory controller125 of FIG. 1 may then identify the pre-programmed pollution pattern touse simply by passing to data chip 305 of FIG. 3 the identifier of theselected pre-programmed pollution pattern.

Note that in FIG. 6, pollution pattern 510 is 32-bits long, whereaspollution patterns 605-630 are four bits long. In some embodiments ofthe inventive concept, pollution patterns (such as pollution pattern510) that have the same width as buffer 320 of FIG. 3 may be used,whereas in other embodiments of the inventive concepts pollutionpatterns (such as pollution pattern 605) that have narrower widths thanbuffer 320 of FIG. 3 may be used, with the pattern repeated as often asnecessary to establish a pollution pattern that covers the entirety ofbuffer 320 of FIG. 3. The advantage of using a fine granularity(full-width) pollution pattern is increased flexibility in establishingand using the pollution pattern; the disadvantage of a fine granularitypollution pattern is that mask register 335 of FIG. 3 would need tostore more information, and the pollution pattern is potentially lessreliable. The advantage of a coarse granularity (narrow-width) pollutionpattern is that it is not as wide as buffer 320 of FIG. 3 and thereforerequires fewer bits in mask register 335 of FIG. 3; a coarse granularitypollution patterns is also potentially more reliable. The disadvantageof a coarse granularity pollution pattern is that the pollution patternis less flexible and the number of possible pollution patterns islimited.

Note that, ideally, the number of bits in common between any pair ofpollution patterns used in the memory module should be no more than onehalf of the number bits in the pollution pattern. For example, if twopollution patterns are identical except for a value in a single bit, anerror that affects that bit could leave memory controller 125 of FIG. 1unable to determine which data chip had the error. Increasing the numberof bits that differ between pollution patterns increases the likelihoodthat memory controller 125 of FIG. 1 may identify which data chip hasthe error. Thus, for any pair of pollution patterns 605, 610, 615, 620,625, and 630, only two of the four bits are the same, keeping thepollution patterns as far apart as possible.

FIG. 7 shows details of memory controller 125 of FIG. 1. In FIG. 7,memory controller 125 is shown as including pollution patternprogramming circuitry 705, read circuitry 710, parity circuitry 715,pollution pattern determination circuitry 720, pollution patternanalysis circuitry 725, error correction logic 730, and log 735.Pollution pattern programming circuitry 705 may program a data chip,such as data chip 305 of FIG. 3, of memory module 115 of FIG. 1, with apollution pattern. As described above with reference to FIG. 6,pollution pattern programming circuitry 705 may program a particularpollution pattern (of either fine granularity or coarse granularity)into data chip 305 of FIG. 3, or pollution pattern programming circuitry705 may identify a pre-programmed pollution pattern (again, of eitherfine granularity or coarse granularity) for data chip 305 of FIG. 3 touse. Pollution pattern programming circuitry 705 is typically used onboot up of the machine, with the programmed pollution pattern remainingunchanged in data chip 305 of FIG. 3 until the machine is booted upagain, although embodiments of the inventive concept may supportchanging the programmed pollution patterns at any time.

In other embodiments of the inventive concept, data chips 305 of FIG. 3may be programmed by the manufacturer of memory module 115 of FIG. 1with pollution patterns. In such an embodiment of the inventive concept,it is assumed that each data chip in a particular channel has a uniquepollution pattern. (Data chips in different channels may bedistinguished by their channel, so data chips in different channelsmight have the same pollution pattern.) That way, when polluted data isdetected, the particular chip with the error may (hopefully) beidentified.

During normal operations, read circuitry 710 may send requests to readdata from memory module 115 of FIG. 1, which may then be received bymemory controller 125. Parity circuitry 715 may then perform a paritycalculation on the data received from the data chips. If there were noerrors reading the data from the data chips (or any errors weresuccessfully corrected internally to the data chips), then the result ofparity circuitry 715 should indicate no parity errors in the datareceived, and memory controller 125 may deliver the data to the host orother entity requesting the data.

But if the result of parity circuitry 715 indicates that there is aparity error, then memory controller 125 may attempt to correct theerror. Pollution pattern analysis circuitry 725 may compare the resultof parity circuitry 715 with the pollution patterns programmed into datachips 305 of FIG. 3 to see if a match (or a near match) may be found. Ifa match (or a near match) may be found, then error correction circuitry730 may attempt to correct the error using information across all datachips 305 of FIG. 3 in memory module 115 of FIG. 1. If the error may notbe corrected for any reason, log 735 may store information about theerror.

FIG. 8 shows memory controller 125 of FIG. 3 performing a paritycalculation on data from data chips 305 of FIG. 3 in memory 115 ofFIG. 1. In FIG. 8, original data 805, 810, 815, and so on throughoriginal data 820 may represent data from the various data chips inmemory module 115 of FIG. 1. In FIG. 8, data from a total of 9 datachips are shown, but embodiments of the inventive concept may supportdata from any number of data chips. Note that one or more of data chips305 of FIG. 3 may be the results from an in-chip ECC: original data 805,810, 815, and 820 do not need to be strictly from chips that store realdata.

Parity 825 is the result of calculating the parity of original data 805,810, 815, and 820. Parity 825 may be calculated in any desired manner:in FIG. 8, parity 825 is calculated as the XOR of original data 805,810, 815, and 820. If parity 825 is all zeroes, then memory controller125 of FIG. 1 may conclude that there is no error in any of data chips305 of FIG. 3. But if parity 825 has any ones (indicating a parityerror), then that result indicates that there is at least one data chip305 of FIG. 3 that has an error. Note that since one (or more) of thedata chips will have had an uncorrectable error, the data fromthat/those chip(s) will be polluted by the pollution pattern(s)associated with the data chip(s).

The above description assumes that parity 825 includes all zeroes whenthere is no error. If parity 825 is calculated according to a differentprinciple (e.g., all ones indicates no error), then the description maybe adjusted as appropriate to fit the method of calculating parity 825.

Assuming that parity 825 indicates that one data chip 305 of FIG. 3 hasan error, memory controller 125 of FIG. 1 needs to determine which datachip has the error. Pollution pattern analysis circuitry 725 of FIG. 7,whose operation is shown in FIG. 9, performs this analysis. As shown inFIG. 9, pollution pattern analysis circuitry 725 may receive parity 825,along with pollution patterns 605, 610, 615, 620, 625, and 630. AlthoughFIG. 9 shows six pollution patterns, embodiments of the inventiveconcept may support any number of pollution patterns. Pollution patternanalysis circuitry 725 may compare parity 825 with each of pollutionpatterns 605, 610, 615, 620, 625, and 630, and may attempt to determinepollution pattern is the closest to parity 825. The result of thiscomparison may be result 905.

Note that pollution pattern analysis circuitry 725 is described asattempting to determine the pollution pattern “closest” to parity 825.There are two reasons for this statement. First, the data chip with theerror might include one or more errors that prevents parity 825 fromexactly matching any of the programmed pollution patterns. For example,the error might force a particular bit to an incorrect value. In thatcase, that incorrect bit might look like data pollution even though thebit is not part of the pollution pattern, or it might look like a bitthat was not part of the pollution pattern, even though it was polluted.Second, because of data errors, parity 825 might be sufficiently farfrom any programmed pollution pattern that pollution pattern analysiscircuitry 725 may not definitively determine which pollution pattern wasused (and therefore which data chip has the error).

The solutions to these problems are twofold. First, pollution patternanalysis circuitry 725 may select the programmed pollution pattern thatis closest to—that is, has the most bits matching—parity 825. (Thiscomparison may be done either by matching all bits—both zeroes andones—or just bits that are ones in the pollution pattern.) For example,parity 825 matches two bits of programmed pollution patterns 605, 610,and 620, and one bit of programmed pollution patterns 615, 625, and 630.While this might seem to be inconclusive, recall that each data chip 305of FIG. 3 provides more than four bits of data. Thus, while pollutionpatterns 605, 610, 615, 620, 625, and 630 are repeated to cover theentirety of the data from the data chips, the number of errorsthemselves are not likely to repeat with the same frequency as thepollution pattern. For example, assuming that the data chip that had theerror was the data chip that provided original data 805. In that case,the first two bits of parity 825 were contributed by the pollutionpattern, whereas the third bit of parity 825 was due to data error. Ifthe third bit is the only bit with a data error, then parity 825 wouldactually match all of the bits in the pollution pattern associated withthe first data chip.

Second, pollution pattern analysis circuitry 725 may include threshold910. Threshold 910 may specify a maximum distance—that is, number ofdifferent bits—between parity 825 and programmed pollution patterns 605,610, 615, 620, 625, and 630. Provided that parity 825 is withinthreshold 910 of at least one of programmed pollution patterns 605, 610,615, 620, 625, and 630, then the programmed pollution pattern that isclosest to parity 825 may be selected. And if no pollution pattern iswithin threshold 910 of parity 825, memory controller 125 of FIG. 1,then memory controller 125 of FIG. 1 may conclude that the error may notbe corrected. Threshold 910 may be set to any desired distance: forexample, one half of the size of buffer 320 of FIG. 3 (which, of course,is equivalent to the size of the data received by memory controller 125of FIG. 1 from data chip 305 of FIG. 3 and the size of parity 825) orone half the size of the pollution patterns (when the pollution patternhas fewer bits than buffer 320 of FIG. 3). But embodiments of theinventive concept may support other thresholds as well. Another criteriathat may be used to determine threshold 910 may be the minimum number ofbits of difference between any two programmed pollution patterns(considering the programmed pollution patterns to be repeated as neededto completely pollute buffer 320 of FIG. 3).

While FIGS. 8-9 describe using parity 825 as the source of data used toidentify a pollution pattern, embodiments of the inventive concept maysupport other mechanisms to identify a pollution pattern. For example,instead of using parity 825, memory controller 125 of FIG. 7 may includea pollution pattern determination circuitry. The pollution patterndetermination circuitry may perform any desired calculation on any orall of original data 805, 810, 815, and 820 of FIG. 8 to calculate adetermined pollution pattern, which may then be compared with theprogrammed pollution patterns by pollution pattern analysis circuitry725. In such an embodiment of the inventive concept, parity 825, may beused solely to determine if there is an error, whereas the pollutionpattern determination circuitry may be used to determine what isexpected to be the pollution pattern used by the data chip with theerror.

FIG. 10 shows memory controller 125 of FIG. 3 removing the pollutionpattern from parity 825 of FIG. 8 received from a data chip. In FIG. 10,after pollution pattern analysis circuitry 725 of FIG. 7 has determinedthat the pollution pattern used was pollution pattern 605 of FIG. 6,memory controller 125 of FIG. 3 may remove pollution pattern 605 fromparity 825. If pollution pattern 605 was added to the raw data by XORingthe raw data with pollution pattern 605, then pollution pattern 605 maybe removed from parity 825 by XORing pollution pattern 605 with parity825. If a different technique was used to pollute the raw data by thedata chip, then a corresponding technique may be used to remove thepollution pattern from parity 825. Regardless of the technique used, theresult is error 1005: the set of bits that are actually in error. Oncethese bits have been identified in error 1005, these bits may becorrected.

One way to correct the bits is to use the original data from all theother data chips (including the parity data), to reconstruct theoriginal bits that are in error from the data chip. This correction maybe handled at the bit level, using any desired approach: for example,using parity information and the corresponding bits from the other datachips, the original bit in error may be reconstructed. But it may besimpler to just discard the data from the data chip with the error, andinstead reconstruct the entirety of the data from the data chip with theerror. FIG. 11 shows this approach.

In FIG. 11, the data for the data chip with the error (for example,original data 805 of FIG. 8) has been discarded. The entire data for thedata chip with the error may be reconstructed from original data 810,815, and so on through original data 820. Since the original data 810815, and 820 may include information from a parity chip, original data810, 815, and so on through 820 may include enough information toreconstruct the correct information for the data chip with the error.That is, by XORing original data 810, 815, and so on through 820, theresult may recover the original data from the data chip with the error.

FIG. 11 shows how to reconstruct the original data from the data chipwith the error where data from a parity chip is included. If some othertechnique is used to provide for error correction, the technique shownin FIG. 11 may be modified appropriately.

FIGS. 12A-12B show a flowchart of an example procedure for data chip 305of FIG. 3 in memory module 115 of FIG. 1 to pollute data, according toan embodiment of the inventive concept. In FIG. 12A, at block 1205, datachip 305 of FIG. 3 may store a pollution pattern as instructed by memorycontroller 125 of FIG. 1. Block 1205 may be performed only upon theinitial boot up of the system, rather than every time a memory access isperformed. FIG. 13, described below, provides more details about howdata chip 305 of FIG. 3 may store a pollution pattern. At block 1210,data chip 305 of FIG. 3 may receive a request for a value at a memoryaddress from memory controller 125 of FIG. 1. This request may be partof a broader request for a value stored across all the data chips inmemory module 115 of FIG. 1, as opposed to a request for data that islocated solely within a single data chip or a request for data at thatparticular bit. At block 1215, buffer 320 of FIG. 3 may buffer the dataretrieved from DRAM array 310 of FIG. 3. At block 1220, data chip 305 ofFIG. 3 may determine if the data in buffer 320 of FIG. 3 contains anerror. For example, data chip 305 of FIG. 3 might perform a paritycalculation on the bits in buffer 320 of FIG. 3 to determine if there isan error, or ECC engine 325 of FIG. 3 might indicate that there is anerror. If data chip 305 of FIG. 3 determines that there is no error,then at block 1225 transmission circuitry 345 of FIG. 3 may transmit theraw data to memory controller 125 of FIG. 1.

But if in block 1220 data chip 305 of FIG. 3 determines that there is anerror, then at block 1230 (FIG. 12B) data chip 305 of FIG. 3 maydetermine if the error may be corrected using ECC engine 325 of FIG. 3.If the error is correctable, then at block 1235 ECC engine 325 of FIG. 3may correct the error, after which at block 1240 the corrected data maybe sent to memory controller 125 of FIG. 1 via transmission circuitry345 of FIG. 3. Otherwise, at block 1245, data chip 305 of FIG. 3 mayaccess a pollution pattern from mask register 335 of FIG. 3. At block1250, data pollution engine 330 of FIG. 3 may pollute the data in buffer320 of FIG. 3 using the accessed pollution pattern. As described abovewith reference to FIG. 3, polluting the data may be accomplished byXORing the data in buffer 320 of FIG. 3 with the pollution pattern.Finally, at block 1255, transmission circuitry 345 of FIG. 3 maytransmit the polluted data to memory controller 125 of FIG. 1.

FIG. 13 shows a flowchart of an example procedure for data chip 305 inmemory module 115 of FIG. 1 to be programmed with a pollution pattern,according to an embodiment of the inventive concept. In FIG. 13, atblock 1305, data chip 305 of FIG. 3 may receive a pollution pattern frommemory controller 125 of FIG. 1, and at block 1310, data chip 305 ofFIG. 3 may store the received pollution pattern in mask register 335 ofFIG. 3. Alternatively, at block 1315, data chip 305 of FIG. 3 mayreceive an identifier of a pollution pattern than has beenpre-programmed into mask register 335 of FIG. 3, and at block 1320 datachip 305 of FIG. 3 may locate the identified pollution pattern in maskregister 335 of FIG. 3 for use in polluting data when necessary.

FIG. 14 shows a flowchart of an example procedure for data chip 305 ofFIG. 3 in memory module 115 of FIG. 1 to transmit original data tomemory controller 125 of FIG. 1, according to an embodiment of theinventive concept. As described above with reference to FIG. 3, memorycontroller 125 of FIG. 1 may transmit Memory Controller Disable signal355 to data pollution engine 330. Memory Controller Disable signal 355of FIG. 3 provides for a mechanism by which memory controller 125 ofFIG. 1 may receive the raw data (i.e., unpolluted data) from buffer 320of FIG. 3 when data pollution engine 330 of FIG. 3 might otherwisepollute data that contains an uncorrectable error. Memory ControllerDisable signal 355 of FIG. 3 may be useful, for example, in situationswhere the pollution pattern may not be removed from the polluted datafor some reason and memory controller 125 of FIG. 1 wants the unpolluteddata.

In FIG. 14 at block 1405, data chip 305 of FIG. 3 may receive MemoryController Disable signal 355 of FIG. 3. At block 1225 (functionally thesame as block 1225 of FIG. 12A), transmission circuitry 345 of FIG. 3may transmit the raw (unpolluted) data from buffer 320 of FIG. 3 tomemory controller 125 of FIG. 1.

FIG. 14 may be thought of as a variation of blocks 1220-1225 of FIG.12A. For example, the test performed in block 1220 of FIG. 12A may be atwo-part test: first, is the raw data in buffer 320 of FIG. 3error-free; and second, did data chip 305 of FIG. 3 receive MemoryController Disable signal 355 of FIG. 3 from memory controller 125 ofFIG. 1? If either part of the test result in an affirmative answer, thentransmission circuitry 345 of FIG. 3 may transmit the raw data frombuffer 320 of FIG. 3; otherwise, processing may continue with block 1230of FIG. 12B.

FIGS. 15A-15B show a flowchart of an example procedure for memorycontroller 125 of FIG. 1 to perform error correction when data chip 305in memory module 115 of FIG. 1 pollutes data using a pollution pattern,according to an embodiment of the inventive concept. In FIG. 15A, atblock 1505, memory controller 125 of FIG. 1 may program data chip 305 ofFIG. 3 with a pollution pattern. In block 1505, memory controller 125 ofFIG. 1 may select any desired pollution pattern, of either fine orcoarse granularity. Alternatively, at block 1510, memory controller 125of FIG. 1 may select the identifier of a pre-programmed pollutionpattern, and at block 1515, memory controller 125 of FIG. 1 may programdata chip 305 of FIG. 3 with the selected identifier. Like block 1205 ofFIG. 12A, blocks 1505-1510 may be performed only upon the initial bootup of the system, rather than every time a memory access is performed.

Regardless of how memory controller 125 of FIG. 1 programs data chip 305of FIG. 3 with a pollution pattern, at block 1520, read circuitry 710 ofFIG. 7 may receive original data from data chip 305 of FIG. 3. At block1525, parity circuitry 715 of FIG. 7 may calculate parity 825 of FIG. 8.At block 1530, memory controller 125 of FIG. 1 may determine if there isan error in the original data (based on parity 825 of FIG. 8). Asdescribed above, calculating parity 825 of FIG. 8 is one way, but notthe only way, to determine if there is an error in the original data,and embodiments of the inventive concept may support using othertechniques to determine if there is an error in the original data.

At block 1535 (FIG. 15B), memory controller 125 of FIG. 1 decides ifthere is an error in the original data. If there is no error in theoriginal data, then at block 1540 memory controller 125 of FIG. 1 maytransmit the original data to the processor. Otherwise, at block 1545,pollution pattern analysis circuitry 725 of FIG. 7 may attempt toidentify the pollution pattern in parity 825. At block 1550, memorycontroller 125 may use the identified pollution pattern to identify datachip 305 of FIG. 3 with the error. At block 1555, error correctioncircuitry 730 of FIG. 7 may correct the error in data chip 305 of FIG.3. Finally, at block 1560, memory controller 125 of FIG. 1 may transmitthe corrected data to the host.

FIG. 16 shows a flowchart of an example procedure for pollution patternanalysis circuitry 725 of FIG. 7 to identify which pollution pattern wasused to pollute the data, according to an embodiment of the inventiveconcept. In FIG. 16, at block 1525 (functionally similar to block 1525of FIG. 15A, and in fact the two blocks may be a single operation),parity 825 of FIG. 8 may be calculated, to produce a computed pollutionpattern. At block 1605, pollution pattern analysis circuitry 725 of FIG.7 may compare the computed pollution pattern with the pollution patternsassociated with the data chips in memory module 115 of FIG. 1. At block1610, pollution pattern analysis circuitry 725 of FIG. 7 may determineif any of the pollution patterns associated with the data chips inmemory module 115 of FIG. 1 are within a threshold distance of thecomputed pollution pattern. As described above with reference to FIG. 9,the distance may be measured as the number of bits that differ betweenthe computed pollution pattern and the programmed pollution patterns,and the threshold may be any desired threshold.

If the computed pollution pattern is not within a threshold distance ofany of the programmed pollution patterns, then at block 1615, memorycontroller 125 of FIG. 1 may decide not to identify a pollution pattern,and at block 1620, memory controller 125 of FIG. 1 may log the error asan uncorrectable error (UE) in log 735 of FIG. 7. Otherwise, at block1625, pollution pattern analysis circuitry 725 of FIG. 7 may identifythe pollution pattern that is closest to the computed pollution pattern,and thereby identify the data chip with the error.

FIG. 17 shows a flowchart of an example procedure for error correctioncircuitry 730 of FIG. 7 to correct for the error in data chip 305 ofFIG. 3 in memory module 115 of FIG. 1, according to an embodiment of theinventive concept. In FIG. 17, at block 1705, error correction circuitry730 of FIG. 7 may discard the data from data chip 305 with the error. Atblock 1710, error correction circuitry 730 of FIG. 7 may calculate aparity from the other data chips in memory module 115 of FIG. 1, and atblock 1715, error correction circuitry 730 of FIG. 7 may use thecalculated parity as the data from the identified data chip.

Alternatively, at block 1720, error correction circuitry 730 of FIG. 7may remove the pollution pattern from the original data from data chip305 of FIG. 3 with the error. At block 1725, error correction circuitry730 of FIG. 7 may calculate a parity using the unpolluted data from datachip 305 of FIG. 3 with the error, and at block 1730, error correctioncircuitry 730 of FIG. 7 may reverse the bits in the unpolluted databased on the calculated parity.

FIG. 18 shows a flowchart of an example procedure for memory controller125 of FIG. 1 to request the original data from data chip 305 in memorymodule 115 of FIG. 1, according to an embodiment of the inventiveconcept. In FIG. 18, at block 1805, memory controller 125 of FIG. 1 maysend Memory Controller Disable signal 355 of FIG. 3 to data chip 305 ofFIG. 3. At block 1810, memory controller 125 of FIG. 1 may receive theraw data from data chip 305 of FIG. 3

In FIGS. 12A-18, some embodiments of the inventive concept are shown.But a person skilled in the art will recognize that other embodiments ofthe inventive concept are also possible, by changing the order of theblocks, by omitting blocks, or by including links not shown in thedrawings. All such variations of the flowcharts are considered to beembodiments of the inventive concept, whether expressly described ornot.

The following discussion is intended to provide a brief, generaldescription of a suitable machine or machines in which certain aspectsof the inventive concept may be implemented. The machine or machines maybe controlled, at least in part, by input from conventional inputdevices, such as keyboards, mice, etc., as well as by directivesreceived from another machine, interaction with a virtual reality (VR)environment, biometric feedback, or other input signal. As used herein,the term “machine” is intended to broadly encompass a single machine, avirtual machine, or a system of communicatively coupled machines,virtual machines, or devices operating together. Exemplary machinesinclude computing devices such as personal computers, workstations,servers, portable computers, handheld devices, telephones, tablets,etc., as well as transportation devices, such as private or publictransportation, e.g., automobiles, trains, cabs, etc.

The machine or machines may include embedded controllers, such asprogrammable or non-programmable logic devices or arrays, ApplicationSpecific Integrated Circuits (ASICs), embedded computers, smart cards,and the like. The machine or machines may utilize one or moreconnections to one or more remote machines, such as through a networkinterface, modem, or other communicative coupling. Machines may beinterconnected by way of a physical and/or logical network, such as anintranet, the Internet, local area networks, wide area networks, etc.One skilled in the art will appreciate that network communication mayutilize various wired and/or wireless short range or long range carriersand protocols, including radio frequency (RF), satellite, microwave,Institute of Electrical and Electronics Engineers (IEEE) 802.11,Bluetooth®, optical, infrared, cable, laser, etc.

Embodiments of the present inventive concept may be described byreference to or in conjunction with associated data including functions,procedures, data structures, application programs, etc. which whenaccessed by a machine results in the machine performing tasks ordefining abstract data types or low-level hardware contexts. Associateddata may be stored in, for example, the volatile and/or non-volatilememory, e.g., RAM, ROM, etc., or in other storage devices and theirassociated storage media, including hard-drives, floppy-disks, opticalstorage, tapes, flash memory, memory sticks, digital video disks,biological storage, etc. Associated data may be delivered overtransmission environments, including the physical and/or logicalnetwork, in the form of packets, serial data, parallel data, propagatedsignals, etc., and may be used in a compressed or encrypted format.Associated data may be used in a distributed environment, and storedlocally and/or remotely for machine access.

Embodiments of the inventive concept may include a tangible,non-transitory machine-readable medium comprising instructionsexecutable by one or more processors, the instructions comprisinginstructions to perform the elements of the inventive concepts asdescribed herein.

Having described and illustrated the principles of the inventive conceptwith reference to illustrated embodiments, it will be recognized thatthe illustrated embodiments may be modified in arrangement and detailwithout departing from such principles, and may be combined in anydesired manner. And, although the foregoing discussion has focused onparticular embodiments, other configurations are contemplated. Inparticular, even though expressions such as “according to an embodimentof the inventive concept” or the like are used herein, these phrases aremeant to generally reference embodiment possibilities, and are notintended to limit the inventive concept to particular embodimentconfigurations. As used herein, these terms may reference the same ordifferent embodiments that are combinable into other embodiments.

The foregoing illustrative embodiments are not to be construed aslimiting the inventive concept thereof. Although a few embodiments havebeen described, those skilled in the art will readily appreciate thatmany modifications are possible to those embodiments without materiallydeparting from the novel teachings and advantages of the presentdisclosure. Accordingly, all such modifications are intended to beincluded within the scope of this inventive concept as defined in theclaims.

Embodiments of the inventive concept may extend to the followingstatements, without limitation:

Statement 1. An embodiment of the inventive concept includes a datachip, comprising:

a data array;

read circuitry to read raw data from the data array;

a buffer to store the raw data read from the data array by the readcircuitry;

a mask register to store a pollution pattern;

a data pollution engine to modify the raw data stored in the bufferusing the pollution pattern stored in the mask register to produce apolluted data; and

transmission circuitry to transmit the polluted data from the buffer.

Statement 2. An embodiment of the inventive concept includes a data chipaccording to statement 1, wherein the data chip is included in a DynamicRandom Access Memory (DRAM) module.

Statement 3. An embodiment of the inventive concept includes a data chipaccording to statement 1, wherein:

the data chip is included in a Dynamic Random Access Memory (DRAM)module the DRAM module including a plurality of other data chips, and

the pollution pattern stored the mask register of the data chip (305)differs from pollution patterns stored in the plurality of other datachips in the DRAM module.

Statement 4. An embodiment of the inventive concept includes a data chipaccording to statement 1, wherein the transmission circuitry isoperative to transmit the polluted data to a memory controller.

Statement 5. An embodiment of the inventive concept includes a data chipaccording to statement 1, wherein:

the data chip further comprises an error correcting code (ECC) circuitryto perform error correction on the raw data stored in the buffer; and

the data pollution engine is operative to modify the raw data stored inthe buffer using the pollution pattern stored in the mask register whenthe ECC circuitry detects but may not correct an error in the raw datastored in the buffer.

Statement 6. An embodiment of the inventive concept includes a data chipaccording to statement 1, wherein the data pollution engine includes XORcircuitry to perform an XOR operation on the raw data stored in thebuffer and the pollution pattern stored in the mask register.

Statement 7. An embodiment of the inventive concept includes a data chipaccording to statement 1, wherein the data pollution engine is operativeto modify the raw data stored in the buffer using the pollution patternstored in the mask register unless the data pollution engine receives aMemory Controller Disable signal from a memory controller.

Statement 8. An embodiment of the inventive concept includes a data chipaccording to statement 1, wherein the pollution pattern is programmedinto the mask register inside the data chip by a memory controller onboot up.

Statement 9. An embodiment of the inventive concept includes a data chipaccording to statement 1, wherein:

the pollution pattern is one of a plurality of pre-programmed pollutionpatterns stored in the mask register; and

the data chip may receive from the memory controller 125 an identifierof the pollution pattern to use from the mask register.

Statement 10. An embodiment of the inventive concept includes a memorycontroller, comprising:

read circuitry to request a value at an address stored in a plurality ofdata chips;

parity circuitry to calculate a parity from original data received fromthe plurality of the data chips;

pollution pattern analysis circuitry to compare the parity with aplurality of pollution patterns programmed into the plurality of thedata chips to identify a data chip with an error; and

error correction circuitry to correct the error in the original datareceived from the identified data chip with the error.

Statement 11. An embodiment of the inventive concept includes a memorycontroller according to statement 10, wherein the plurality of datachips are included in a Dynamic Random Access Memory (DRAM) module.

Statement 12. An embodiment of the inventive concept includes a memorycontroller according to statement 10, wherein the pollution patternanalysis circuitry and the error correction circuitry are utilized onlyif the parity circuitry indicates that there is an error in the originaldata received from the plurality of the data chips.

Statement 13. An embodiment of the inventive concept includes a memorycontroller according to statement 12, wherein the calculated parity fromthe original data received from the plurality of the data chipsindicates if there is an error in the original data received from theplurality of the data chips.

Statement 14. An embodiment of the inventive concept includes a memorycontroller according to statement 10, wherein the pollution patternanalysis circuitry is operative to identify one of the plurality ofpollution patterns programmed into the plurality of the data chips thatis closest to the parity.

Statement 15. An embodiment of the inventive concept includes a memorycontroller according to statement 14, wherein the pollution patternanalysis circuitry is further operative to determine if the identifiedone of the pollution patterns programmed into the plurality of the datachips is within a threshold of the parity.

Statement 16. An embodiment of the inventive concept includes a memorycontroller according to statement 15, wherein the threshold is one halfof a size of the parity.

Statement 17. An embodiment of the inventive concept includes a memorycontroller according to statement 15, wherein the pollution patternanalysis circuitry is further operative to not identify any of thepollution patterns programmed into the plurality of the data chips ifnone of the pollution patterns programmed into the plurality of the datachips is within the threshold of the parity.

Statement 18. An embodiment of the inventive concept includes a memorycontroller according to statement 17, further comprising a log to logthat none of the pollution patterns programmed into the plurality of thedata chips is within the threshold of the parity.

Statement 19. An embodiment of the inventive concept includes a memorycontroller according to statement 14, wherein the pollution patternanalysis circuitry is operative to identify the one of the plurality ofpollution patterns programmed into the plurality of the data chips thathas the most bits that match bits in the parity pollution pattern.

Statement 20. An embodiment of the inventive concept includes a memorycontroller according to statement 14, wherein the pollution patternanalysis circuitry is operative to identify one of the plurality of thedata chips associated with the identified one of the plurality ofpollution patterns programmed into the plurality of the data chips asthe identified data chip with the error.

Statement 21. An embodiment of the inventive concept includes a memorycontroller according to statement 14, wherein:

the memory controller is operative to send the identified data chip withthe error a Memory Controller Disable signal; and

the read circuitry is operative to receive a raw data from theidentified data chip with the error.

Statement 22. An embodiment of the inventive concept includes a memorycontroller according to statement 10, wherein the error correctioncircuitry is operative to recreate the data from the identified datachip with the error using the original data from the others of theplurality of the data chips.

Statement 23. An embodiment of the inventive concept includes a memorycontroller according to statement 22, wherein the parity circuitry isoperative to recreate the data from the identified data chip with theerror by calculating a parity for the original data from others of theplurality of the data chips.

Statement 24. An embodiment of the inventive concept includes a memorycontroller according to statement 10, wherein the error correctioncircuitry is operative to remove the parity from the original datareceived from the identified data chip with the error and to correct theerror in the unpolluted data from the identified data chip with theerror using the unpolluted data from the identified data chip with theerror and the original data from others of the plurality of the datachips.

Statement 25. An embodiment of the inventive concept includes a memorycontroller according to statement 24, wherein the error correctioncircuitry is further operative to calculate a parity for the unpolluteddata from the identified data chip with the error and the original datafrom others of the plurality of the data chips and to reverse at leastone bit in the unpolluted data from the identified data chip with theerror based on the calculated parity.

Statement 26. An embodiment of the inventive concept includes a memorycontroller according to statement 10, further comprising pollutionpattern programming circuitry to select a plurality of pollutionpatterns for the plurality of the data chips during boot up.

Statement 27. An embodiment of the inventive concept includes a memorycontroller according to statement 26, wherein the plurality of pollutionpatterns are all unique.

Statement 28. An embodiment of the inventive concept includes a memorycontroller according to statement 26, wherein the pollution patternprogramming circuitry is operative to program the plurality of the datachips with the plurality of pollution patterns during the boot up.

Statement 29. An embodiment of the inventive concept includes a memorycontroller according to statement 26, wherein the pollution patternprogramming circuitry is operative to select a plurality of identifiersof pre-programmed pollution patterns for the plurality of the data chipsduring the boot up and to program the plurality of the data chips withthe selected plurality of identifiers during the boot up.

Statement 30. An embodiment of the inventive concept includes a method,comprising

receiving at a data chip a request for value at an address;

buffering raw data in a buffer of the data chip, the raw data includingthe value at the address;

determining if the raw data in the buffer has an error; and

if the raw data in the buffer has an error:

-   -   polluting the raw data in the buffer using a pollution pattern        to produce a polluted data; and    -   sending the polluted data in the buffer to a memory controller.

Statement 31. An embodiment of the inventive concept includes a methodaccording to statement 30, wherein polluting the raw data in the bufferusing a pollution pattern includes XORing the raw data in the bufferwith the pollution pattern.

Statement 32. An embodiment of the inventive concept includes a methodaccording to statement 30, further comprising, if the raw data in thebuffer does not have an error, sending the raw data in the buffer to thememory controller.

Statement 33. An embodiment of the inventive concept includes a methodaccording to statement 30, wherein the data chip is included in aDynamic Random Access Memory (DRAM) module.

Statement 34. An embodiment of the inventive concept includes a methodaccording to statement 30, further comprising, if the raw data in thebuffer has an error:

determining if the error in the raw data in the buffer may be corrected;and

if the error in the raw data in the buffer may not be corrected:

-   -   polluting the raw data in the buffer using the pollution        pattern; and    -   sending the polluted data in the buffer to the memory        controller.

Statement 35. An embodiment of the inventive concept includes a methodaccording to statement 34, further comprising, if the error in the rawdata in the buffer may be corrected:

correcting the raw data in the buffer; and

sending the corrected data in the buffer to the memory controller.

Statement 36. An embodiment of the inventive concept includes a methodaccording to statement 30, wherein polluting the raw data in the bufferusing a pollution pattern includes accessing the pollution pattern froma mask register in the data chip.

Statement 37. An embodiment of the inventive concept includes a methodaccording to statement 36, further comprising:

receiving the pollution pattern from the memory controller; and

storing the received pollution pattern in the mask register.

Statement 38. An embodiment of the inventive concept includes a methodaccording to statement 36, wherein:

the method further comprises receiving a pollution pattern identifierfrom the memory controller; and

accessing the pollution pattern from a mask register in the data chipincludes accessing the pollution pattern from the mask register in thedata chip responsive to the pollution pattern identifier.

Statement 39. An embodiment of the inventive concept includes a methodaccording to statement 30, wherein the pollution pattern includes afirst width equal to a second width of the buffer.

Statement 40. An embodiment of the inventive concept includes a methodaccording to statement 30, wherein the pollution pattern includes afirst width less than a second width of the buffer, the pollutionpattern repeated to be at least as wide as the buffer.

Statement 41. An embodiment of the inventive concept includes a methodaccording to statement 30, further comprising:

receiving a Memory Controller Disable signal at the data chip; and

sending the raw data in the buffer to the memory controller.

Statement 42. An embodiment of the inventive concept includes a method,comprising:

receiving original data from a plurality of data chips;

determining if the original data from at least one of the plurality ofthe data chips has an error;

if the original data from at least one of the plurality of the datachips has the error:

-   -   attempting to identify a pollution pattern using the original        data from the plurality of the data chips;    -   using the pollution pattern to identify the at least one of the        plurality of the data chips that has the error; and    -   correcting the error in the original data from the plurality of        the data chips responsive to the pollution pattern and the        original data from the plurality of the data chips.

Statement 43. An embodiment of the inventive concept includes a methodaccording to statement 42, wherein plurality of the data chips areincluded in a Dynamic Random Access Memory (DRAM) module.

Statement 44. An embodiment of the inventive concept includes a methodaccording to statement 42, further comprising transmitting the correcteddata to a host.

Statement 45. An embodiment of the inventive concept includes a methodaccording to statement 42, wherein, if the original data from at leastone of the plurality of the data chips does not have the error,transmitting the original data to a host.

Statement 46. An embodiment of the inventive concept includes a methodaccording to statement 42, wherein determining if the original data fromat least one of the plurality of the data chips has an error includes:

performing a parity calculation on the original data from the pluralityof the data chips; and

determining if the original data from the at least one of the pluralityof the data chips has the error if the parity calculation indicates aparity error.

Statement 47. An embodiment of the inventive concept includes a methodaccording to statement 42, wherein attempting to identify a pollutionpattern using the original data from the plurality of the data chipsincludes:

computing a pollution pattern from the original data from the pluralityof the data chips;

comparing the computed pollution pattern with a plurality of pollutionpatterns associated with the plurality of the data chips; and

if one of the plurality of the pollution patterns associated with theplurality of the data chips is within a threshold of the computedpollution pattern, identifying the pollution pattern that is within athreshold of the computed pollution pattern.

Statement 48. An embodiment of the inventive concept includes a methodaccording to statement 47, wherein comparing the computed pollutionpattern with a plurality of pollution patterns associated with theplurality of the data chips includes identifying the one of theplurality of the pollution patterns associated with the plurality of thedata chips that is closest to the computed pollution pattern.

Statement 49. An embodiment of the inventive concept includes a methodaccording to statement 48, wherein identifying the one of the pluralityof the pollution patterns associated with the plurality of the datachips that is closest to the computed pollution pattern includesidentifying the one of the plurality of the pollution patternsassociated with the plurality of the data chips that has the most bitsthat match bits in the computed pollution pattern.

Statement 50. An embodiment of the inventive concept includes a methodaccording to statement 47, wherein the threshold is one half of a sizeof the computed pollution pattern.

Statement 51. An embodiment of the inventive concept includes a methodaccording to statement 47, wherein if none of the plurality of thepollution patterns associated with the plurality of the data chips iswithin the threshold of the computed pollution pattern, not identifyingany pollution pattern associated with the plurality of the data chips.

Statement 52. An embodiment of the inventive concept includes a methodaccording to statement 51, further comprising logging the error as anuncorrectable error (UE).

Statement 53. An embodiment of the inventive concept includes a methodaccording to statement 47, further comprising:

sending the identified at least one of the plurality of the data chipsthat has the error a Memory Controller Disable signal; and

receiving a raw data from the identified at least one of the pluralityof the data chips that has the error.

Statement 54. An embodiment of the inventive concept includes a methodaccording to statement 47, wherein correcting the error in the originaldata from the plurality of the data chips responsive to the pollutionpattern and the original data from the plurality of the data chipsincludes:

discarding the original data from the identified at least one of theplurality of the data chips that has the error; and

recreating the data from the identified at least one of the plurality ofthe data chips that has the error using the original data from theothers of the plurality of the data chips.

Statement 55. An embodiment of the inventive concept includes a methodaccording to statement 54, wherein recreating the data from theidentified at least one of the plurality of the data chips that has theerror using the original data from the others of the plurality of thedata chips includes:

calculating a parity for the original data from the others of theplurality of the data chips; and

using the calculated parity as the data from the identified at least oneof the plurality of the data chips that has the error.

Statement 56. An embodiment of the inventive concept includes a methodaccording to statement 47, wherein correcting the error in the originaldata from the plurality of the data chips responsive to the pollutionpattern and the original data from the plurality of the data chipsincludes:

removing the identified pollution pattern from the original data fromthe identified at least one of the plurality of the data chips that hasthe error, producing unpolluted data; and

correcting the error in the unpolluted data from the identified at leastone of the plurality of the data chips that has the error using theunpolluted data from the identified at least one of the plurality of thedata chips that has the error and the original data from the others ofthe plurality of the data chips.

Statement 57. An embodiment of the inventive concept includes a methodaccording to statement 56, wherein removing the identified pollutionpattern from the original data from the identified at least one of theplurality of the data chips that has the error, producing unpolluteddata includes XORing the identified pollution pattern with the originaldata from the identified at least one of the plurality of the data chipsthat has the error.

Statement 58. An embodiment of the inventive concept includes a methodaccording to statement 56, wherein correcting the error in theunpolluted data from the identified at least one of the plurality of thedata chips that has the error using the unpolluted data from theidentified at least one of the plurality of the data chips that has theerror and the original data from the others of the plurality of the datachips includes:

calculating a parity for the unpolluted data from the identified atleast one of the plurality of the data chips that has the error and theoriginal data from the others of the plurality of the data chips; and

reversing at least one bit in the unpolluted data from the identified atleast one of the plurality of the data chips that has the error based onthe calculated parity.

Statement 59. An embodiment of the inventive concept includes a methodaccording to statement 42, further comprising selecting a plurality ofpollution patterns for the plurality of the data chips during boot up.

Statement 60. An embodiment of the inventive concept includes a methodaccording to statement 59, wherein selecting a plurality of pollutionpatterns for the plurality of the data chips includes programming theplurality of the data chips with the plurality of pollution patternsduring the boot up.

Statement 61. An embodiment of the inventive concept includes a methodaccording to statement 59, wherein selecting a plurality of pollutionpatterns for the plurality of the data chips includes:

selecting a plurality of identifiers of pre-programmed pollutionpatterns for the plurality of the data chips during the boot up; and

programming the plurality of the data chips with the selected pluralityof identifiers during the boot up.

Statement 62. An embodiment of the inventive concept includes anarticle, comprising a tangible storage medium, the tangible storagemedium having stored thereon non-transitory instructions that, whenexecuted by a machine, result in

receiving at a data chip a request for value at an address;

buffering raw data in a buffer of the data chip, the raw data includingthe value at the address;

determining if the raw data in the buffer has an error; and

if the raw data in the buffer has an error:

-   -   polluting the raw data in the buffer using a pollution pattern        to produce a polluted data; and    -   sending the polluted data in the buffer to a memory controller.

Statement 63. An embodiment of the inventive concept includes an articleaccording to statement 62, wherein polluting the raw data in the bufferusing a pollution pattern includes XORing the raw data in the bufferwith the pollution pattern.

Statement 64. An embodiment of the inventive concept includes an articleaccording to statement 62, the tangible storage medium having storedthereon further non-transitory instructions that, when executed by themachine, result in, if the raw data in the buffer does not have anerror, sending the raw data in the buffer to the memory controller.

Statement 65. An embodiment of the inventive concept includes an articleaccording to statement 62, wherein the data chip is included in aDynamic Random Access Memory (DRAM) module.

Statement 66. An embodiment of the inventive concept includes an articleaccording to statement 62, the tangible storage medium having storedthereon further non-transitory instructions that, when executed by themachine, result in, if the raw data in the buffer has an error:

determining if the error in the raw data in the buffer may be corrected;and

if the error in the raw data in the buffer may not be corrected:

-   -   polluting the raw data in the buffer using the pollution        pattern; and    -   sending the polluted data in the buffer to the memory        controller.

Statement 67. An embodiment of the inventive concept includes an articleaccording to statement 66, the tangible storage medium having storedthereon further non-transitory instructions that, when executed by themachine, result in, if the error in the raw data in the buffer may becorrected:

correcting the raw data in the buffer; and

sending the corrected data in the buffer to the memory controller.

Statement 68. An embodiment of the inventive concept includes an articleaccording to statement 62, wherein polluting the raw data in the bufferusing a pollution pattern includes accessing the pollution pattern froma mask register in the data chip.

Statement 69. An embodiment of the inventive concept includes an articleaccording to statement 68, the tangible storage medium having storedthereon further non-transitory instructions that, when executed by themachine, result in:

receiving the pollution pattern from the memory controller; and

storing the received pollution pattern in the mask register.

Statement 70. An embodiment of the inventive concept includes an articleaccording to statement 68, wherein:

the method further comprises receiving a pollution pattern identifierfrom the memory controller; and

accessing the pollution pattern from a mask register in the data chipincludes accessing the pollution pattern from the mask register in thedata chip responsive to the pollution pattern identifier.

Statement 71. An embodiment of the inventive concept includes an articleaccording to statement 62, wherein the pollution pattern includes afirst width equal to a second width of the buffer.

Statement 72. An embodiment of the inventive concept includes an articleaccording to statement 62, wherein the pollution pattern includes afirst width less than a second width of the buffer, the pollutionpattern repeated to be at least as wide as the buffer.

Statement 73. An embodiment of the inventive concept includes an articleaccording to statement 62, the tangible storage medium having storedthereon further non-transitory instructions that, when executed by themachine, result in:

receiving a Memory Controller Disable signal at the data chip; and

sending the raw data in the buffer to the memory controller.

Statement 74. An embodiment of the inventive concept includes anarticle, comprising a tangible storage medium, the tangible storagemedium having stored thereon non-transitory instructions that, whenexecuted by a machine, result in:

receiving original data from a plurality of data chips;

determining if the original data from at least one of the plurality ofthe data chips has an error;

if the original data from at least one of the plurality of the datachips has the error:

-   -   attempting to identify a pollution pattern using the original        data from the plurality of the data chips;    -   using the pollution pattern to identify the at least one of the        plurality of the data chips that has the error; and    -   correcting the error in the original data from the plurality of        the data chips responsive to the pollution pattern and the        original data from the plurality of the data chips.

Statement 75. An embodiment of the inventive concept includes an articleaccording to statement 74, wherein plurality of the data chips areincluded in a Dynamic Random Access Memory (DRAM) module.

Statement 76. An embodiment of the inventive concept includes an articleaccording to statement 74, the tangible storage medium having storedthereon further non-transitory instructions that, when executed by themachine, result in transmitting the corrected data to a host.

Statement 77. An embodiment of the inventive concept includes an articleaccording to statement 74, wherein, if the original data from at leastone of the plurality of the data chips does not have the error,transmitting the original data to a host.

Statement 78. An embodiment of the inventive concept includes an articleaccording to statement 74, wherein determining if the original data fromat least one of the plurality of the data chips has an error includes:

performing a parity calculation on the original data from the pluralityof the data chips; and

determining if the original data from the at least one of the pluralityof the data chips has the error if the parity calculation indicates aparity error.

Statement 79. An embodiment of the inventive concept includes an articleaccording to statement 74, wherein attempting to identify a pollutionpattern using the original data from the plurality of the data chipsincludes:

computing a pollution pattern from the original data from the pluralityof the data chips;

comparing the computed pollution pattern with a plurality of pollutionpatterns associated with the plurality of the data chips; and

if one of the plurality of the pollution patterns associated with theplurality of the data chips is within a threshold of the computedpollution pattern, identifying the pollution pattern that is within athreshold of the computed pollution pattern.

Statement 80. An embodiment of the inventive concept includes an articleaccording to statement 79, wherein comparing the computed pollutionpattern with a plurality of pollution patterns associated with theplurality of the data chips includes identifying the one of theplurality of the pollution patterns associated with the plurality of thedata chips that is closest to the computed pollution pattern.

Statement 81. An embodiment of the inventive concept includes an articleaccording to statement 80, wherein identifying the one of the pluralityof the pollution patterns associated with the plurality of the datachips that is closest to the computed pollution pattern includesidentifying the one of the plurality of the pollution patternsassociated with the plurality of the data chips that has the most bitsthat match bits in the computed pollution pattern.

Statement 82. An embodiment of the inventive concept includes an articleaccording to statement 79, wherein the threshold is one half of a sizeof the computed pollution pattern.

Statement 83. An embodiment of the inventive concept includes an articleaccording to statement 79, wherein if none of the plurality of thepollution patterns associated with the plurality of the data chips iswithin the threshold of the computed pollution pattern, not identifyingany pollution pattern associated with the plurality of the data chips.

Statement 84. An embodiment of the inventive concept includes an articleaccording to statement 83, the tangible storage medium having storedthereon further non-transitory instructions that, when executed by themachine, result in logging the error as an uncorrectable error (UE).

Statement 85. An embodiment of the inventive concept includes an articleaccording to statement 79, the tangible storage medium having storedthereon further non-transitory instructions that, when executed by themachine, result in:

sending the identified at least one of the plurality of the data chipsthat has the error a Memory Controller Disable signal; and

receiving a raw data from the identified at least one of the pluralityof the data chips that has the error.

Statement 86. An embodiment of the inventive concept includes an articleaccording to statement 79, wherein correcting the error in the originaldata from the plurality of the data chips responsive to the pollutionpattern and the original data from the plurality of the data chipsincludes:

discarding the original data from the identified at least one of theplurality of the data chips that has the error; and

recreating the data from the identified at least one of the plurality ofthe data chips that has the error using the original data from theothers of the plurality of the data chips.

Statement 87. An embodiment of the inventive concept includes an articleaccording to statement 86, wherein recreating the data from theidentified at least one of the plurality of the data chips that has theerror using the original data from the others of the plurality of thedata chips includes:

calculating a parity for the original data from the others of theplurality of the data chips; and

using the calculated parity as the data from the identified at least oneof the plurality of the data chips that has the error.

Statement 88. An embodiment of the inventive concept includes an articleaccording to statement 79, wherein correcting the error in the originaldata from the plurality of the data chips responsive to the pollutionpattern and the original data from the plurality of the data chipsincludes:

removing the identified pollution pattern from the original data fromthe identified at least one of the plurality of the data chips that hasthe error, producing unpolluted data; and

correcting the error in the unpolluted data from the identified at leastone of the plurality of the data chips that has the error using theunpolluted data from the identified at least one of the plurality of thedata chips that has the error and the original data from the others ofthe plurality of the data chips.

Statement 89. An embodiment of the inventive concept includes an articleaccording to statement 88, wherein removing the identified pollutionpattern from the original data from the identified at least one of theplurality of the data chips that has the error, producing unpolluteddata includes XORing the identified pollution pattern with the originaldata from the identified at least one of the plurality of the data chipsthat has the error.

Statement 90. An embodiment of the inventive concept includes an articleaccording to statement 88, wherein correcting the error in theunpolluted data from the identified at least one of the plurality of thedata chips that has the error using the unpolluted data from theidentified at least one of the plurality of the data chips that has theerror and the original data from the others of the plurality of the datachips includes:

calculating a parity for the unpolluted data from the identified atleast one of the plurality of the data chips that has the error and theoriginal data from the others of the plurality of the data chips; and

reversing at least one bit in the unpolluted data from the identified atleast one of the plurality of the data chips that has the error based onthe calculated parity.

Statement 91. An embodiment of the inventive concept includes an articleaccording to statement 74, the tangible storage medium having storedthereon further non-transitory instructions that, when executed by themachine, result in selecting a plurality of pollution patterns for theplurality of the data chips during boot up.

Statement 92. An embodiment of the inventive concept includes an articleaccording to statement 91, wherein selecting a plurality of pollutionpatterns for the plurality of the data chips includes programming theplurality of the data chips with the plurality of pollution patternsduring the boot up.

Statement 93. An embodiment of the inventive concept includes an articleaccording to statement 91, wherein selecting a plurality of pollutionpatterns for the plurality of the data chips includes:

selecting a plurality of identifiers of pre-programmed pollutionpatterns for the plurality of the data chips during the boot up; and

programming the plurality of the data chips with the selected pluralityof identifiers during the boot up.

Consequently, in view of the wide variety of permutations to theembodiments described herein, this detailed description and accompanyingmaterial is intended to be illustrative only, and should not be taken aslimiting the scope of the inventive concept. What is claimed as theinventive concept, therefore, is all such modifications as may comewithin the scope and spirit of the following claims and equivalentsthereto.

What is claimed is:
 1. A memory controller, comprising: read circuitryto request a value at an address stored in a plurality of data chips;parity circuitry to calculate a parity from original data received fromthe plurality of the data chips; pollution pattern analysis circuitry tocompare the parity with a plurality of pollution patterns programmedinto the plurality of the data chips to identify a data chip with anerror; and error correction circuitry to correct the error in theoriginal data received from the identified data chip with the error. 2.The memory controller according to claim 1, wherein the plurality ofdata chips are included in a Dynamic Random Access Memory (DRAM) module.3. The memory controller according to claim 1, wherein the pollutionpattern analysis circuitry and the error correction circuitry areutilized only based at least in part on the parity circuitry indicatingthat there is an error in the original data received from the pluralityof the data chips.
 4. The memory controller according to claim 3,wherein the calculated parity from the original data received from theplurality of the data chips indicates that there is an error in theoriginal data received from the plurality of the data chips.
 5. Thememory controller according to claim 1, wherein the pollution patternanalysis circuitry is operative to identify one of the plurality ofpollution patterns programmed into the plurality of the data chips thatis closest to the parity.
 6. The memory controller according to claim 5,wherein the pollution pattern analysis circuitry is further operative todetermine that the identified one of the pollution patterns programmedinto the plurality of the data chips is within a threshold of theparity.
 7. The memory controller according to claim 6, wherein thethreshold is one half of a size of the parity.
 8. The memory controlleraccording to claim 6, wherein the pollution pattern analysis circuitryis further operative to not identify any of the pollution patternsprogrammed into the plurality of the data chips based at least in parton none of the pollution patterns programmed into the plurality of thedata chips being within the threshold of the parity.
 9. The memorycontroller according to claim 8, further comprising a log to log thatnone of the pollution patterns programmed into the plurality of the datachips is within the threshold of the parity.
 10. The memory controlleraccording to claim 5, wherein the pollution pattern analysis circuitryis operative to identify the one of the plurality of pollution patternsprogrammed into the plurality of the data chips that has the most bitsthat match bits in the parity pollution pattern.
 11. The memorycontroller according to claim 5, wherein the pollution pattern analysiscircuitry is operative to identify one of the plurality of the datachips associated with the identified one of the plurality of pollutionpatterns programmed into the plurality of the data chips as theidentified data chip with the error.
 12. The memory controller accordingto claim 5, wherein: the memory controller is operative to send theidentified data chip with the error a Memory Controller Disable signal;and the read circuitry is operative to receive a raw data from theidentified data chip with the error.
 13. The memory controller accordingto claim 1, wherein the error correction circuitry is operative torecreate the data from the identified data chip with the error using theoriginal data from the others of the plurality of the data chips. 14.The memory controller according to claim 13, wherein the paritycircuitry is operative to recreate the data from the identified datachip with the error by calculating a parity for the original data fromothers of the plurality of the data chips.
 15. The memory controlleraccording to claim 1, wherein the error correction circuitry isoperative to remove the parity from the original data received from theidentified data chip with the error and to correct the error in theunpolluted data from the identified data chip with the error using theunpolluted data from the identified data chip with the error and theoriginal data from others of the plurality of the data chips.
 16. Thememory controller according to claim 15, wherein the error correctioncircuitry is further operative to calculate a parity for the unpolluteddata from the identified data chip with the error and the original datafrom others of the plurality of the data chips and to reverse at leastone bit in the unpolluted data from the identified data chip with theerror based on the calculated parity.
 17. The memory controlleraccording to claim 1, further comprising pollution pattern programmingcircuitry to select a plurality of pollution patterns for the pluralityof the data chips during boot up.
 18. The memory controller according toclaim 17, wherein the plurality of pollution patterns are all unique.19. The memory controller according to claim 17, wherein the pollutionpattern programming circuitry is operative to program the plurality ofthe data chips with the plurality of pollution patterns during the bootup.
 20. The memory controller according to claim 17, wherein thepollution pattern programming circuitry is operative to select aplurality of identifiers of pre-programmed pollution patterns for theplurality of the data chips during the boot up and to program theplurality of the data chips with the selected plurality of identifiersduring the boot up.